View CBTL02042ABQ_1260600.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description cbtl02042a/b is a 2 differential channel, 2-to -1 multiplexer/ demultiplexer switch for pci express generation 2 (gen2), and other high-speed serial interface applications. the cbtl02042a/b can switch two differential si gnals to one of two locations. using a unique design technique, nxp has minimized the im pedance of the switch such that the attenuation observed through the switch is negligible, and also minimized the channel-to-channel skew as well as channel-to-channel crosstalk, as required by the high-speed serial interface. cbtl02042a/b allows expansion of existing high speed ports for extremely low power. the device's pinouts are optimized to match different application layouts. cbtl02042a has input and output pins on the opposite of the package, and is suitable for edge connector(s) with different signal sources on the motherboard. cbtl02042b has outputs on both sides of the package, and the device can be placed between two connectors to multiplex differential signals from a controller. please refer to section 8 for layout examples. 2. features and benefits ? 2 bidirectional differential channel, 2 : 1 multiplexer/demultiplexer ? high-speed signal switching for pcie gen2 5 gbit/s ? high bandwidth: 7 ghz at ? 3db ? low insertion loss: ? ? 0.5 db at 100 mhz ? ? 1.2 db at 2.5 ghz ? low intra-pair skew: 5 ps typical ? low inter-pair skew: 35 ps maximum ? low crosstalk: ? 30 db at 2.5 ghz ? low off-state isolation: ? 25 db at 2.5 ghz ? low return loss: ? 20 db at 2.5 ghz ? v dd operating range: 3.3 v 10 % ? shutdown pin (xsd) for power-saving mode ? standby current less than 1 a ? esd tolerance: ? 8kv hbm ? 1 kv cdm ? dhvqfn20 package cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 multiplexer/demultiplexer switch for pc i express gen2 rev. 1 ? 10 march 2011 product data sheet
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 2 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 3. applications ? routing of high-speed differential signals with low signal attenuation ? pcie gen2 ? displayport 1.2 ? usb 3.0 ? sata 6 gbit/s 4. ordering information [1] total height after printed-circuit board mounting = 1.0 mm maximum. 5. functional diagram table 1. ordering information type number package name description version CBTL02042ABQ dhvqfn20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 4.5 0.85 mm [1] sot764-1 cbtl02042bbq dhvqfn20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 4.5 0.85 mm [1] sot764-1 fig 1. functional diagram of cbtl02042a; cbtl02042b 002aaf07 3 b0_p b0_n b1_p b1_n a0_p a0_n a1_p a1_n c0_p c0_n c1_p c1_n sel xsd
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 3 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 6. pinning information 6.1 pinning 6.2 pin description a. cbtl02042a b. cbtl02042b fig 2. pin configuration for dhvqfn20 002aaf761 cbtl02042a transparent top view c1_n a1_n sel c1_p a1_p c0_n v dd c0_p gnd b1_n a0_n b1_p a0_p b0_n xsd b0_p v dd gnd v dd gnd 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 10 11 1 20 terminal 1 index area 002aaf762 cbtl02042b transparent top view sel c1_p c1_n b1_n a1_n b1_p a1_p gnd c0_n v dd c0_p b0_n a0_n b0_p a0_p xsd gnd v dd gnd v dd 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 10 11 1 20 terminal 1 index area table 2. pin description symbol pin type description cbtl02042a cbtl02042b a0_p 3 2 i/o channel 0, port a differential signal input/output a0_n 4 3 i/o a1_p 7 6 i/o channel 1, port a differential signal input/output a1_n 8 7 i/o b0_p 19 18 i/o channel 0, port b differential signal input/output b0_n 18 17 i/o b1_p 17 14 i/o channel 1, port b differential signal input/output b1_n 16 13 i/o c0_p 15 4 i/o channel 0, port c differential signal input/output c0_n 14 5 i/o c1_p 13 8 i/o channel 1, port c differential signal input/output c1_n 12 9 i/o sel 9 12 cmos single-ended input operation mode select sel = low: a ? b sel = high: a ? c
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 4 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 [1] dhvqfn20 package die supply ground is connected to both gnd pins and exposed center pad. gnd pins and the exposed center pad must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board level performanc e, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. 7. functional description refer to figure 1 ? functional diagram of cbtl02042a; cbtl02042b ? . 7.1 function selection and shutdown function the cbtl02042a/b provides a shutdown function to minimize power consumption when the application is not active, but power to the cbtl02042a/b is provided. the xsd pin (active high) places all ch annels in high-impedance st ate (non-conducting) while reducing current consumption to near-zero. when xsd pin is low, the device operates normally. xsd 2 19 cmos single-ended input shutdown pin; should be driven low or connected to v ss for normal operation. when high, all paths are switched off (non-conducting high-impedance state), and supply current consumption is minimized. v dd 1, 6, 10 11, 16, 20 power positive supply voltage, 3.3 v ( 10 %) gnd [1] 5, 11, 20, center pad 1, 10, 15, center pad power supply ground table 2. pin description ?continued symbol pin type description cbtl02042a cbtl02042b table 3. function selection x = don?t care. xsd sel function high x an, bn and cn pins are high-z low low an to bn and vice versa low high an to cn and vice versa
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 5 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 8. application design-in information fig 3. applications using cbtl02042a fig 4. application using cbtl02042b 002aaf776 mini card/ msata connector cbtl02042a esata controller pcie controller esata/usb 3.0 combo connector cbtl02042a esata controller usb 3.0 controller 002aaf777 usb 3.0 connector cbtl02042b usb 3.0 controller usb 3.0 connector
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 6 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 9. limiting values [1] human body model: ansi/eos/esd-s5.1-1994, standard for esd sensitivity testing, human body model - component level; electrostatic disc harge association, rome, ny, usa. [2] charged device model: ansi/eos/esd-s5.3-1-1999, stand ard for esd sensitivity testing, charged device model - component level; electrostatic discharge association, rome, ny, usa. 10. recommended operating conditions 11. static characteristics [1] typical values are at v dd = 3.3 v, t amb =25 c, and maximum loading. [2] input leakage current is 50 a if differential pairs are pulled to high and low. table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.3 +4.6 v t case case temperature ? 40 +85 c v esd electrostatic discharge voltage hbm [1] - 8000 v cdm [2] - 1000 v table 5. recommended operating conditions symbol parameter conditions min typ max unit v dd supply voltage 3.0 3.3 3.6 v v i input voltage - - v dd v t amb ambient temperature oper ating in free air ? 40 - +85 c table 6. static characteristics v dd = 3.3 v 10 %; t amb = ? 40 c to +85 c; unless otherwise specified. symbol parameter conditions min typ [1] max unit i dd supply current v dd = max.; v i =gndorv dd ; xsd = low -1.352.5ma i stb standby current v dd = max.; v i =gndorv dd ; xsd = high --1 a i ih high-level input current v dd = max.; v i =v dd -- 5 [2] a i il low-level input current v dd = max.; v i =gnd - - 5 [2] a v ih high-level input voltage sel, xsd pins 0.65v dd -- v v il low-level input voltage sel, xsd pins - - 0.35v dd v v i input voltage differential pins - - 2.4 v sel, xsd pins - - v dd v v ic common-mode input voltage 0-2.0v v id differential input voltage peak-to-peak - - 1.6 v
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 7 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 12. dynamic characteristics [1] typical values are at v dd = 3.3 v; t amb =25 c, and maximum loading. table 7. dynamic characteristics v dd =3.3v 10 %; t amb = ? 40 c to +85 c; unless otherwise specified. symbol parameter conditions min typ [1] max unit ddil differential insertion loss channel is off f=100mhz - ? 50 - db f=2.5ghz - ? 25 - db channel is on f=100mhz - ? 0.5 - db f=2.5ghz - ? 1.2 - db ddnext differential near-end crosstalk adjacent channels are on f=100mhz - ? 50 - db f=2.5ghz - ? 30 - db b ? 3db ? 3 db bandwidth - 7.0 - ghz ddrl differential return loss f = 100 mhz - ? 25 - db f=2.5ghz - ? 20 - db r on on-state resistance v dd = 3.3 v; v i =2v; i i =19ma - 6 - t pd propagation delay from port a to port b, or port a to port c, or vice versa -80-ps switching characteristics t startup start-up time supply voltage valid or xsd going low to channel specified operating characteristics --10ms t pzh off-state to high propagation delay - - 300 ns t pzl off-state to low propagation delay - - 70 ns t phz high to off-state propagation delay - - 50 ns t plz low to off-state propagation delay - - 50 ns t sk(dif) differential skew time intra-pair - 5 - ps t sk skew time inter-pair - - 35 ps
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 8 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. output 2 is for an output with internal conditions such that the output is high except when disabled by the output control. the outputs are measured one at a time with one transition per measurement. fig 5. voltage waveforms for enable and disable times 002aag01 3 v dd t plz 0.5v dd 0.5v dd sel output 1 t pzl v ol 0 v 0.85v oh v oh 0.25v oh output 2 t pzh t phz v ol v oh 0.85v oh 0.25v oh
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 9 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 13. test information c l = load capacitance; includes jig and probe capacitance. r t = termination resistance; should be equal to z o of the pulse generator. all input pulses are supplied by generators hav ing the following characteristics: prr 5mhz; z o =50 ; t r 2.5 ns; t f 2.5 ns. fig 6. test circuitry for switching times fig 7. test circuit table 8. test data test load switch c l r l t plz , t pzl (output on b side) 50 pf 200 2 v ic t phz , t pzh (output on b side) 50 pf 200 gnd t pd -200 open pulse generator v o c l 50 pf r l 200 002aag01 4 r t v ic v dd dut r l 200 2 v ic open gnd 002aae65 5 4-port, 20 ghz network analyzer port 1 port 4 dut port 2 port 3
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 10 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 14. package outline fig 8. package outline sot764-1 (dhvqfn20) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 4.6 4.4 d h 3.15 2.85 y 1 2.6 2.4 1.15 0.85 e 1 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot764-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot764- 1 d hvqfn20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 2 0 terminals; body 2.5 x 4.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 29 19 12 11 10 1 20 x d e c b a terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 11 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 15. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 15.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 15.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 12 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 15.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 9 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 9 and 10 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 9 . table 9. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 10. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 13 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 16. abbreviations 17. revision history msl: moisture sensitivity level fig 9. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 11. abbreviations acronym description cdm charged-device model dut device under test esd electrostatic discharge hbm human body model i/o input/output pci peripheral component interconnect pcie pci express prr pulse repetition rate sata serial advanced technology attachment usb universal serial bus table 12. revision history document id release date data sheet status change notice supersedes cbtl02042a_cbtl02042b v.1 20110310 product data sheet - -
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 14 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
cbtl02042a_cbtl02042b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 1 ? 10 march 2011 15 of 16 nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors cbtl02042a; cbtl02042b 3.3 v, 2 differential channel, 2 : 1 mux/demux switch for pcie gen2 ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 10 march 2011 document identifier: cbtl02042a_cbtl02042b please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 4 7.1 function selection and shutdown function . . . . 4 8 application design-in information . . . . . . . . . . 5 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 10 recommended operating conditions. . . . . . . . 6 11 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 12 dynamic characteristics . . . . . . . . . . . . . . . . . . 7 13 test information . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 15 soldering of smd packages . . . . . . . . . . . . . . 11 15.1 introduction to soldering . . . . . . . . . . . . . . . . . 11 15.2 wave and reflow soldering . . . . . . . . . . . . . . . 11 15.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 11 15.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 12 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 18 legal information. . . . . . . . . . . . . . . . . . . . . . . 14 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 18.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 19 contact information. . . . . . . . . . . . . . . . . . . . . 15 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

▲Up To Search▲

Price & Availability of CBTL02042ABQ

	To Download CBTL02042ABQ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .